Recently, a large-scale integrated (LSI) circuit device such as, for example, a microcomputer or a semiconductor memory device finds wide variety of practical applications for its productivity and small occupation space. However, in this situation, it is not enough to build up a practical system by using only standard-type large-scale integrated circuit devices represented by the microcomputer and the semiconductor memory device. Then, custom-made large-scale integrated circuit devices are provided to establish a high-performance system. The custom-made large-scale integrated circuit devices are classified into two groups one of which is called as a full-custom-made large-scale integrated circuit device and the other of which is called as a semi-custom-made large-scale integrated circuit device. The full-custom-made large-scale integrated circuit device is beneficial to a consumer product of the mass-produced type, and the semi-custom-made large-scale integrated circuit device is located between the standard-type large-scale integrated circuit device and the full-custom-made large-scale integrated circuit device and is widely used. The wider it is used, the higher efficiency the user demands to the semi-custom-made large-scale integrated circuit device.
One of the approaches to achieve a higher efficiency appears to be the development of a macro-cell type large-scale integration. The macro-cell type large-scale integration is different from a logic gate array but is fabricated on a semiconductor substrate with function blocks each equivalent in function to a standard type semiconductor integrated circuit device. According to the fabrication process of the macro-cell type large-scale integration, a plurality of function blocks selected from a macro-cell library have been formed with the most appropriate circuit arrangements which in turn have been transferred to the mask layouts. The function block thus prepared without limitation of time occupies a relatively small amount of area on the semiconductor substrate so that the macro-cell type large-scale integration is advantageous in integration density over the logic gate array.
One of the goals in development of the macro-cell type large-scale integration is to establish a diagnostic method after integration process. A typical diagnostic technique is carried out by applying a macro-cell type large-scale integration with a test pattern consisting of a string of binary bits from an analyzer through its testing probes. In detail, FIG. 1 shows a typical example of the macro-cell type large-scale integrated circuit fabricated on a semiconductor substrate 1. The macro-cell type large-scale integrated circuit comprises three function blocks 2, 3 and 4 and each of the function blocks 2, 3 and 4 has a circuit arrangement to achieve a predetermined function and a plurality of probe pads or, alternatively, a plurality of bonding pads one of which is designated by reference numeral 5. The probe pads or the bonding pads are selectively coupled by metal wirings to form a large-scale integrated circuit and the large-scale integrated circuit with the metal wirings is packed into a case ( which is not shown in the drawings ). For diagnosis of the function blocks, the probes are attached to the probe pads or the bonding pads and the respective test patterns are supplied from the analyzer to the function blocks through the probes. However, a problem is encountered in the prior-art diagnostic technique in limited opportunity. Namely, the diagnosis is carried out under directly contacting the probes to the probe pads of the macro-cell type large-scale integrated circuit, then the testing opportunity is limited to a stage before the packaging. However, the macro-cell type large-scale integrated circuit is liable to be subjected to a heat stress and a mechanical stress during the packaging process and, for this reason, some macro-cell type large-scale integrated circuits are deteriorated in characteristics even if no problem is found in the diagnostic operation. Moreover, the diagnostic technique described above has another problem in deterioration of integration density. This is because of the fact that the diagnostic technique requests a plurality of probe pads each having an area sufficient to receive the probe of the analyzer. A large amount of area is consumed by probe pads as shown in FIG. 1 so that the number of transistors formed on the semiconductor substrate is restricted due to a narrow area available for formation.
Another diagnostic technique is carried out by using a function block 6 performing as a central processing unit ( CPU ). Referring to FIG. 2 of the drawings, there is shown another prior-art macro-cell type large-scale integration fabricated on a semiconductor substrate 7. The macro-cell type large-scale integrated circuit illustrated in FIG. 2 further comprises three function blocks 8, 9 and 10 which serve as peripheral circuits of the central processing unit. The function block 6 is coupled to the function blocks 8, 9 and 10 by a plurality of metal wirings so that the function block 6 serving as the central processing unit can control the function blocks 8, 9 and 10 serving as the peripheral circuits based on programmed instructions fed from the outside. The programmed instructions include testing instructions 11 for the function block 8, testing instructions 12 for the function block 9 and testing instructions 13 for the function block 10. When a diagnostic operation starts, the testing instructions 11 for the function block 8 are fed from the outside to the function block 6 and the function block 6 produces a test pattern consisting of a string of binary bits which are applied to the function block 8 so as to diagnose whether or not the function block 8 achieves a predetermined function. Upon accomplishment of the diagnosis for the function block 8, the testing instructions 12 are fed to the function block 6 and the function block 6 produces a test pattern consisting of a string of binary bits for the diagnostic operation for the function block 9. In this manner, diagnostic operations are carried out for all of the function blocks serving as the peripheral circuits. This diagnostic technique provides a solution of the problem inherent in the diagnostic technique described with reference to FIG. 1 because the testing instructions 11, 12 and 13 can be fed from the outside through an input-output port even if the macro-cell large-scale integrated circuit is packed into a case. However, another problem is encountered in the diagnostic technique described with reference to FIG. 2 of the drawings in preparing a large number of testing instructions fed from the outside to the function block serving as a central processing unit. Namely, the macro-cell type large-scale integrated circuit has a variety of function blocks each serving as a central processing unit different in type from that employed in the other macro-cell type integrated circuit device. If the central processing unit is different in type, the instruction codes are also different from those of another central processing unit. As a result, the number of testing instructions TI needed is calculated by the following: EQU TI=CPU.times.PHC
where CPU is the number of the central processing unit types and the PHC is the number of the peripheral circuit types.